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US 2013/0232385 A1Published application
Latency Detection in a Memory Built-In Self-Test by Using a Ping Signal
AssigneeAdvanced Micro Devices, Inc.
InventorsKay Hesse, Suresh Periyacheri
Life of this patent
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Abstract
In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.
Claims15
-11. (canceled)
A method of performing a memory self-test of a memory portion of a semiconductor device, the method comprising:
- determining a round trip latency of control signals and a failure signal exchanged between said memory portion and a memory built-in self-test (MBIST) circuit prior to a first run of a test algorithm, said test algorithm causing said MBIST circuit to perform a plurality of memory operations and compare a result data of said plurality of memory operations with a reference data to determine a plurality of memory failures, wherein determining said round trip latency comprises generating a ping signal and conveying said ping signal on one or more signal lines used for conveying said control and failure signal;
- and
- obtaining a failure bitmap of said memory portion for a selected one of said plurality of memory failures on the basis of said round trip latency by performing a second run of said test algorithm.
(canceled)
A method, comprising:
- sending a ping signal from a test circuit of a semiconductor device to a memory area of said semiconductor device via a control line bus connecting said test circuit with said memory area, said memory area accommodating a memory portion of said semiconductor device;
- passing at least a portion of said ping signal through a latency adaptation circuit so as to obtain a substantially equal process latency for said at least a portion of the ping signal and control and data signals to be processed in said memory area;
- returning said at least a portion of said ping signal to said test circuit via a failure signal line;
- performing a memory self-test algorithm by sending a sequence of memory operations and test data to said memory area via said control line bus and a data line bus;
- and
- controlling an operation counter on the basis of said returned at least a portion of the ping signal and a failure signal that indicates occurrence of a memory failure.
3 more elements
Dependencies are inferred from the claim text.