US 2013/0221418 A1Published application

Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors

AssigneeTexas Instruments Incorporated

InventorsAllan T. Mitchell, Imran Mahmood Khan, Michael A. Wu

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Abstract

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Claims13

Dependent claims

An integrated circuit formed at a semiconductor surface of a body, including an electrically programmable capacitor structure for an analog semiconductor integrated circuit, the integrated circuit comprising:

a plurality of active regions at the semiconductor surface;
gate dielectric film disposed over the plurality of active regions of the semiconductor surface;
a first polysilicon electrode doped to a first conductivity type throughout its length, disposed over the gate dielectric and extending over the plurality of active regions;
a capacitor dielectric film over the first polysilicon electrode;
and
a first conductive plate, comprising a metal and formed in a conductor level, the first conductive plate disposed over a portion of the first polysilicon electrode with the capacitor dielectric film therebetween;
wherein a first active region of the plurality of active regions comprises:
first and second source/drain regions of a second conductivity type opposite to the first conductivity type, disposed at the surface of the first active region on opposing sides of the portion over which the first polysilicon electrode extends;
and
a channel region disposed between the first and second source/drain regions and underlying the first polysilicon electrode and gate dielectric film, the channel region having a surface portion of the first conductivity type and a buried portion of the second conductivity type disposed at a selected depth underlying the first polysilicon electrode;
and wherein a second active region of the plurality of active regions, over a portion of which the first polysilicon electrode is disposed, is of comprises:
first and second source/drain regions of the first conductivity type disposed at the surface of the second active region on opposing sides of the portion over which the first polysilicon electrode extends;
and
a channel region of the second conductivity type disposed between the first and second source/drain regions and underlying the first polysilicon electrode and gate dielectric film.

11 more elements

A method of fabricating an electrically programmable capacitor structure for an analog semiconductor integrated circuit, formed at a semiconductor surface of a body, comprising the steps of:

forming isolation dielectric structures at selected locations of the semiconductor surface, the isolation dielectric structures defining active regions of the surface therebetween;
forming a gate dielectric layer over the active regions;
then forming an electrode layer comprised of polycrystalline silicon overall;
removing selected portions of the electrode layer to define a first electrode comprised of polycrystalline silicon and including a portion overlying an isolation dielectric structure and a plurality of portions overlying active regions;
doping the polycrystalline silicon to a first conductivity type;
performing an ion implantation of dopant of a second conductivity type, opposite to the first conductivity type, into a first active region to define a buried transistor channel;
forming source and drain regions of the second conductivity type on opposite sides of a portion of the first electrode overlying the first active region;
then depositing a dielectric film overall;
then depositing a conductor layer comprising a metal;
and
removing selected portions of the conductor layer to define a first conductive plate overlying the dielectric film and a portion of the first electrode, at a location overlying an isolation dielectric structure.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/406,704Filed 28 Feb 2012
Published: 29 Aug 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10B 41/00
Electrically erasable-and-programmable rom [eeprom] devices comprising floating gates
H10D 1/692
Capacitors having no potential barriers: electrodes
H10D 62/314
Of igfets: having vertical doping variations

Family

US 8,981,445 B2Related patent
US 2013/0221418 A1This patent

From the US filing history. Foreign family members aren’t listed.

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