Self-repairing memory

A computing device comprising:

• a processor;
• and
• a memory macro connected to the processor comprising:
• a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;
• a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;
• a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array;
• and
• a corrected data cache having at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair, the corrected data cache configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

A method of operating a memory, the method comprising:

• detecting an error which occurs during accessing an address in a memory array;
• correcting data corresponding with the detected error;
• storing the corrected data in a corrected data cache;
• associating the corrected data with the address in the memory array;
• outputting the corrected data to circuitry external to the memory;
• determining whether the error is a hard error or a soft error;
• and
• writing the corrected data stored in the corrected data cache back into the memory array if the error is a soft error.