Electronic apparatus and method for memory control
AssigneeSeiko Epson Corporation
InventorTakeshi Saito
Life of this patent
Estimating the term…
Abstract
An electronic apparatus having plural memories of different performances such as bus widths facilitates achievement of its potential as a system. The electronic apparatus has a first memory and a memory controller configured to control the first memory. Upon a second memory being detected, the memory controller compares bus widths of the first memory and the second memory with each other. Upon the bus width of the second memory being broader than the bus width of the first memory, the memory controller makes a setting such that access to the second memory precedes access to the first memory.
Claims10
An electronic apparatus comprising:
- a first memory;
- and
- a memory controller configured to control the first memory, the memory controller being configured to upon a second memory being detected,
- compare bus widths of the first memory and the second memory with each other, and
- make a setting such that access to the second memory precedes access to the first memory upon the bus width of the second memory being broader than the bus width of the first memory.
An electronic apparatus comprising:
- a first memory;
- a memory controller configured to control the first memory;
- and
- a CPU configured to upon a second memory being detected,
- compare bus widths of the first memory and the second memory with each other, and
- make a setting such that access to the second memory precedes access to the first memory upon the bus width of the second memory being broader than the bus width of the first memory.
A method for memory control of an electronic apparatus having a first memory and a memory controller configured to control the first memory, the method comprising:
- comparing, upon a second memory being detected, bus widths of the first memory and the second memory with each other by means of the memory controller;
- and
- making a setting by means of the memory controller such that access to the second memory precedes access to the first memory upon the bus width of the second memory being broader than the bus width of the first memory.
Dependencies are inferred from the claim text.