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US 2013/0170275 A1Published application
Dual port sram having reduced cell size and rectangular shape
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsShishir Kumar, Dibya Dipti, Pierre Malinge
Life of this patent
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Abstract
A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
Claims7
A structure for an SRAM memory cell comprising
- a substrate;
- a first active area that is physically isolated from all other active areas in the memory cell, the first active area being part of a first data storage node and a drain region of a first transistor;
- a second active area that is physically isolated from all other active areas in the memory cell, the second active area being part of a second data storage node and a drain region of a second transistor;
- a third active area that is physically isolated from all other active areas in the memory cell, the third active area forming part of the first data storage node and a drain region of a third transistor;
- a fourth active area that is physically isolated from all other active areas in the memory cell, the fourth active area being part of the second data storage node and drain region of a fourth transistor;
- a fifth active area that is part of the first data storage node and is common physical area shared by a fifth and sixth transistor;
- a sixth active area that is part of the second data storage node and is common physical area shared by a seventh and eighth transistor;
- a first metal layer that electrically connects the first, third and fifth active areas to form the first data storage node;
- and
- a second metal layer that electrically connects the second, fourth and sixth active areas to form the second data storage node.
7 more elements
An SRAM memory cell comprising:
- a substrate;
- a first active area that is physically isolated from all other active areas in the memory cell, the first active area being part of a first data storage node and a drain region of a first transistor;
- a second active area that is physically isolated from all other active areas in the memory cell, the second active area being part of a second data storage node and a drain region of a second transistor;
- a third active area that is physically isolated from all other active areas in the memory cell, the third active area forming part of the first data storage node and a drain region of a third transistor;
- a fourth active area that is physically isolated from all other active areas in the memory cell, the fourth active area being part of the second data storage node and drain region of a fourth transistor;
- a fifth active area that is part of the first data storage node and is part of a fifth transistor;
- and
- a sixth active area that is part of the second data storage node and is part of a sixth transistor.
5 more elements
Dependencies are inferred from the claim text.