Method and apparatus for detecting intrusions in a computer system
AssigneeAdvanced Micro Devices, Inc.
InventorReza Yazdani
Life of this patent
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Abstract
The present invention provides a method and apparatus for detecting intrusions in a processor-based system. One embodiment of the method includes calculating a first checksum from first bits representative of instructions in a block of a program concurrently with executing the instructions. This embodiment of the method also includes issuing a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using second bits representative of instructions in the block when the second checksum is calculated.
Claims25
A method, comprising:
- calculating a first checksum from first bits representative of instructions in a block of a program concurrently with executing the instructions;
- and
- issuing a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using second bits representative of instructions in the block when the second checksum is calculated.
A method, comprising:
- generating a table comprising entries that are indexed by addresses associated with blocks of a program, wherein each entry of the table includes a checksum calculated using bits representative of instructions in the block;
- and
- comparing values of the entries in the table with checksums generated by a processor-based system concurrently with the processor-based system executing the corresponding block of the program.
An apparatus, comprising:
- means for calculating a first checksum from first bits representative of instructions in a block of a program concurrently with executing the instructions;
- and
- means for issuing a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using second bits representative of instructions in the block when the second checksum is calculated.
A computer readable storage medium encoded with instructions that, when executed by a processor-based system, cause the processor-based system to:
- calculate a first checksum from bits representative of instructions in a block of a program concurrently with executing the instructions;
- and
- issue a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using bits representative of instructions in the block.
A processor-based system, comprising:
- at least one processor configured to calculate a first checksum from bits representative of instructions in a block of a program concurrently with executing the instructions;
- a first register for storing the first checksum;
- and
- a second register for storing a value of a second checksum calculated prior to execution of the block using bits representative of instructions in the block, wherein said at least one processor is configured to issue a security exception in response to determining that the first checksum is different than the second checksum.
Dependencies are inferred from the claim text.