Method and apparatus for low latency communication and synchronization for multi-thread applications
OwnerJohn E. Blackinventor
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OwnerJohn E. Blackinventor
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A computing device, a communication/synchronization path or channel apparatus and a method for parallel processing of a plurality of processors. The parallel processing computing device includes a first processor having a first central processing unit (CPU) core, at least one second processor having a second central processing unit (CPU) core, and at least one communication/synchronization (com/syn) path or channel coupled between the first CPU core and the at least one second CPU core. The communication/synchronization channel can include a request message queue configured to receive request messages from the first CPU core and to send request messages to the second CPU core, and a response message queue configured to receive response messages from the second CPU core and to send response messages to the first CPU core.
A parallel processing computing device, comprising:
A communication/synchronization (com/syn) channel apparatus for parallel processing of a plurality of processors, comprising:
A method for parallel processing of a plurality of processors, comprising:
Dependencies are inferred from the claim text.