US 2013/0159955 A1 · DYNAMIC PIN ACCESS MAXIMIZATION FOR MULTI-PATTERNING LITHOGRAPHY

Abstract

A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A cell is placed in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL. A net is routed to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape. The pin shape is modified after routing to resolve the coloring conflict to result in a modified cell.

Claims20

Dependent claims

A computer implemented method for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL), the method comprising:

placing a cell in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL;
routing a net to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape;
and
modifying the pin shape after routing to resolve the coloring conflict to result in a modified cell.

1 more element

A computer usable program product comprising a computer usable storage medium including computer usable code for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL), the computer usable code comprising:

computer usable code for placing a cell in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL;
computer usable code for routing a net to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape;
and
computer usable code for modifying the pin shape after routing to resolve the coloring conflict to result in a modified cell.

1 more element

A data processing system for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL), the data processing system comprising:

a storage device including a storage medium, wherein the storage device stores computer usable program code;
and
a processor, wherein the processor executes the computer usable program code, and wherein the computer usable program code comprises:
computer usable code for placing a cell in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL;
computer usable code for routing a net to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape;
and
computer usable code for modifying the pin shape after routing to resolve the coloring conflict to result in a modified cell.

4 more elements

Dependencies are inferred from the claim text.

Dynamic pin access maximization for multi-patterning lithography

Life of this patent

Dynamic pin access maximization for multi-patterning lithography

Life of this patent

Abstract

Claims20