US 2013/0159952 A1 · COMBINING MULTIPLE TIMING MODES OF INTEGRATED CIRCUIT

Abstract

A method and system for combining multiple timing modes of an integrated circuit. The method includes the steps of: creating logic groups for at least one logic device in the circuit according to at least one clock driving the at least one logic device, performing static timing analysis to the circuit in multiple given timing modes, obtaining at least one relationship between the logic groups in each of the multiple given timing modes according to a result of the static timing analysis, and combining the obtained at least one relationship between the logic groups in each of the multiple given timing modes

Claims15

Dependent claims

A method of combining multiple timing modes of an integrated circuit, the method comprising the steps of:

creating logic groups for at least one logic device in the circuit according to at least one clock driving the at least one logic device;
performing static timing analysis to the circuit in multiple given timing modes;
obtaining at least one relationship between the logic groups in each of the multiple given timing modes according to a result of the static timing analysis;
and
combining the obtained at least one relationship between the logic groups in each of the multiple given timing modes.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/716,501Filed 17 Dec 2012

Priority

CN 201110456741.720 Dec 2011

Published

20 Jun 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/396
Circuit design at the physical level: clock trees

Combining multiple timing modes of integrated circuit

Life of this patent

Combining multiple timing modes of integrated circuit

Life of this patent

Abstract

Claims15