Method and apparatus of an integrated circuit
AssigneeIndustrial Technology Research Institute
InventorsCHANG TZU LIN, DING MING KWAI
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Abstract
A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump
Claims27
A computer-implemented method for interconnect redundancy of a circuit design, comprising the steps of:
- setting Manhattan distance less than or equal to a predetermined value;
- placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side;
- determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance;
- and
- providing a routing path between the at least one interconnecting candidate and the signal bump.
A computer-implemented method for timing analysis of integrated circuit design, comprising the steps of:
- generating a physical layout of an integrated circuit;
- performing interconnect redundancy on the physical layout of the integrated circuit to create a plurality of redundant interconnections, wherein the interconnect redundancy is based on a physical layout of an integrated circuit to be bonded;
- performing a first static timing analysis to compute an first expected timing of the integrated circuit;
- performing a first redundant interconnections removing to remove the redundant interconnections which have timing violations according to the first expected timing;
- and
- outputting a chip layout.
An apparatus for timing analysis of integrated circuit design, comprising:
- a redundant interconnection device configured to provide a plurality of routing paths, each routing path connecting a signal bump on a semiconductor device to one of a plurality of dummy micro bumps on the semiconductor device, and the one of the plurality of dummy micro bumps being distant from the signal bump within a predetermined Manhattan distance;
- a static timing analyzer configured to provide timing information on a circuit on the semiconductor device;
- and
- a redundant interconnection removing device configured to remove a routing path that violates the timing information.
Dependencies are inferred from the claim text.