Memory architecture for read-modify-write operations

An error correcting code memory, comprising:

• one or more memory chips formed on a die;
• and
• a logic chip formed on the die with the one or more memory chips, where the logic chip is to perform at least one of a first operation or a second operation, where the logic chip, when performing the first operation, is to:
• read error correction code protected data from at least one of the one or more memory chips,
• modify the error correcting code protected data,
• compute new error correcting code parity bits associated with the error correcting code protected data, and
• write the modified error correcting code protected data and the new error correcting code parity bits to at least one of the one or more memory chips;
• and
• where the logic chip, when performing the second operation, is to:
• read error correction code protected data from at least one of the one or more memory chips,
• determine whether an error is detected,
• modify the data and/or error correcting code parity bits when an error is detected, and
• write the modified data and/or error correcting code parity bits to at least one of the one or more memory chips.