Error Detection And Correction Of A Data Transmission

An apparatus for error detection and correction of a data transmission, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

• receiving a block of data, the block of data comprising a predefined number of words, each word including a parity bit, the block of data further comprising an error-correcting code (ECC);
• determining, for each word in dependence upon the parity bit of the word, whether the word includes a parity error;
• committing the word if the word does not include a parity error;
• and
• if only one word of the block includes a parity error:
• correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.

A computer program product for error detection and correction of a data transmission, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, carry out the steps of:

• receiving a block of data, the block of data comprising a predefined number of words, each word including a parity bit, the block of data further comprising an error-correcting code (ECC);
• determining, for each word in dependence upon the parity bit of the word, whether the word includes a parity error;
• committing the word if the word does not include a parity error;
• and
• if only one word of the block includes a parity error:
• correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.