Data processing apparatus and method for identifying debug events

A system comprising:

• a data processing apparatus;
• and
• a debugger connected to said data processing apparatus to perform debugging operations;
• the data processing apparatus comprising:
• at least one circuit block that is accessible for debugging by the debugger, each of said at least one circuit block having a set of debug status registers associated therewith, said set of debug status registers including a debug event register which is set by the circuit block to indicate occurrence of a debug event within the circuit block;
• debug interface circuitry via which said debugger is connected to said data processing apparatus, and configured to interface said debugger with said set of debug status registers for each of said at least one circuit block;
• the debug interface circuitry including at least a first portion which is in a first power domain that remains in a fully powered state whilst said debugger is connected to said debug interface circuitry;
• said set of debug status registers associated with each of said at least one circuit block being in a second power domain which is allowed to transition between said fully powered state and at least one low power state whilst said debugger is connected to said debug interface circuitry, content of said debug status registers only being accessible to the debugger via the debug interface circuitry when said second power domain is in said fully powered state;
• and
• at least one debug attention register provided within said first power domain in association with said first portion of the debug interface circuitry, said at least one debug attention register configured to provide information identifying whether the debug event register provided within the set of debug status registers for any of said at least one circuit block is set;
• the debugger being configured to perform a polling routine to detect said debug events, said polling routine comprising, in a first stage, performing periodic polling of said at least one debug attention register to retrieve data from said at least one debug attention register;
• the polling routine remaining in said first stage whilst the retrieved data from said at least one debug attention register indicates that no debug event register is set;
• and
• when the retrieved data from said at least one debug attention register indicates that the debug event register provided within the set of debug status registers for any of said at least one circuit block is set, the polling routine moves to a second stage during
• which polling of the debug status registers is performed by the debugger to identify the debug event.

A method of identifying debug events within a data processing apparatus, the data processing apparatus having at least one circuit block that is accessible for debugging by a debugger coupled to the data processing apparatus, each of said at least one circuit block having a set of debug status registers associated therewith, said set of debug status registers including a debug event register which is set by the circuit block to indicate occurrence of a debug event within the circuit block, the method comprising:

• connecting said debugger to debug interface circuitry of said data processing apparatus, and configuring the debug interface circuitry to interface said debugger with said set of debug status registers for each of said at least one circuit block;
• arranging at least a first portion of the debug interface circuitry to be in a first power domain that remains in a fully powered state whilst said debugger is connected to said debug interface circuitry;
• arranging said set of debug status registers associated with each of said at least one circuit block to be in a second power domain that is allowed to transition between said fully powered state and at least one low power state whilst said debugger is connected to said debug interface circuitry, content of said debug status registers only being accessible to the debugger via the debug interface circuitry when said second power domain is in said fully powered state;
• providing at least one debug attention register within said first power domain in association with said first portion of the debug interface circuitry, and configuring said at least one debug attention register to provide information identifying whether the debug event register provided within the set of debug status registers for any of said at least one circuit block is set;
• performing a polling routine in the debugger to detect said debug events, said polling routine comprising, in a first stage, performing periodic polling of said at least one debug attention register to retrieve data from said at least one debug attention register;
• retaining the polling routine in said first stage whilst the retrieved data from said at least one debug attention register indicates that no debug event register is set;
• and
• when the retrieved data from said at least one debug attention register indicates that the debug event register provided within the set of debug status registers for any of said at least one circuit block is set, transitioning the polling routine to a second stage during which polling of the debug status registers is performed by the debugger to identify the debug event.

A data processing apparatus comprising:

• at least one circuit block means for access by debugger means coupled to the data processing apparatus, each of said at least one circuit block means having a set of debug status register means associated therewith, said set of debug status register means including a debug event register means for setting by the circuit block means to indicate occurrence of a debug event within the circuit block means;
• debug interface means for connecting said debugger means to said data processing apparatus, and for interfacing said debugger means with said set of debug status register means for each of said at least one circuit block means;
• the debug interface means including at least a first portion which is in a first power domain that remains in a fully powered state whilst said debugger means is connected to said debug interface means;
• said set of debug status register means associated with each of said at least one circuit block means being in a second power domain which is allowed to transition between said fully powered state and at least one low power state whilst said debugger means is connected to said debug interface means, content of said debug status register means only being accessible to the debugger means via the debug interface means when said second power domain is in said fully powered state;
• and
• at least one debug attention register means provided within said first power domain in association with said first portion of the debug interface means, said at least one debug attention register means for providing information identifying whether the debug event register means provided within the set of debug status register means for any of said at least one circuit block means is set;
• whereby polling performed by the debugger means to detect debug events is performed in respect of said at least one debug attention register means, and only if a result of such polling indicates that the debug event register means provided within the set of debug status register means for any of said at least one circuit block means is set is polling of the debug status register means then performed by the debugger means to identify the debug event.