US 2013/0159775 A1 · Debug Registers for Halting Processor Cores after Reset or Power Off

Abstract

A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Claims10

Dependent claims

A method comprising

a power control unit selectively removing power from a first of a plurality of functional units of an integrated circuit (IC) during a debug operation independently of removing power from other ones of the plurality of functional units;
programming a first register to a first value, wherein said programming is performed through the debug port;
restoring power to the first functional unit;
and
halting operation of the first functional unit responsive to restoring power to the first functional unit when the first register is programmed to the first value, wherein the halting is delayed until the restoring in the case that the programming occurs prior to the removing of power.

2 more elements

Dependencies are inferred from the claim text.

Debug Registers for Halting Processor Cores after Reset or Power Off

Life of this patent

Debug Registers for Halting Processor Cores after Reset or Power Off

Life of this patent

Abstract

Claims10