Memory array clock gating scheme

A method for reducing power consumption in a processing device including a processor component and a memory component, the processing component and the memory component synchronized with a system clock, the method comprising:

• processing an instruction within the processor component, the instruction associated with a predetermined memory operation;
• generating a clock enable value associated with one or more memory interface signals for the instruction, the clock gate enable value generated for the instruction prior to an execution stage of an instruction processing sequence;
• driving the clock enable value to a clock gate enable signal associated with the one or more memory interface signals;
• and
• receiving the clock gate enable signal at a clock gate element and generating a gated system clock based on the clock gate enable signal and the system clock, the one or more memory interface signals synchronized by the gated system clock.

A computer system, comprising:

• a processor for synchronously processing instructions according to an instruction processing sequence, wherein processing an instruction includes determining a memory access operation associated with the instruction, the processing further including computing a memory operation enable signal based at an execution stage of the instruction processing sequence;
• a memory component coupled to the processor through a memory control interface;
• and
• a clock gating signal associated with one or more memory interface signals of the memory control interface, the one or more memory interface signals associated with the memory access operation, wherein a clock gate enable value for the clock gating signal is computed prior to the execution stage of the instruction processing sequence.