Method and apparatus for transitioning a system to an active disconnect state

A processor, comprising:

• a processor core;
• and
• a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a processor, comprising:

• a processor core;
• and
• a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.