Providing Hint Register Storage For A Processor
OwnerJames E. McCormick, JR., Dale Morrisinventors
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Abstract
In one embodiment, the present invention includes a method for receiving a data access instruction and obtaining an index into a data access hint register (DAHR) register file of a processor from the data access instruction, reading hint information from a register of the DAHR register file accessed using the index, and performing the data access instruction using the hint information. Other embodiments are described and claimed.
Claims29
A processor comprising:
- at least one execution unit to execute instructions;
- a register file having a first plurality of registers each to store an operand for use in execution of an instruction;
- and
- a hint register file having a second plurality of registers each to store a set of fields each to store a hint value for use by a logic of the processor.
A method comprising:
- receiving a data access instruction in a logic of a processor and obtaining an index into a data access hint register (DAHR) register file of the processor from the data access instruction, the DAHR register file including a plurality of data access hint registers;
- reading hint information from a data access hint register of the DAHR register file accessed using the index;
- and
- performing the data access instruction using the hint information.
A system comprising:
- a processor including a logic to receive a first instruction including an immediate data and to access at least one hint field of a first hint register of a hint register file using the immediate data, wherein the logic is to optimize execution of the first instruction according to a value of the at least one hint field, the processor further including the hint register file and a general purpose register file including a plurality of registers each to store an operand for an instruction;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
A machine-readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving a first instruction of an instruction set architecture (ISA), the first instruction including an identifier of a first hint register of a hint register file of a processor and further including a first value;
- and
- storing the first value in the first hint register responsive to the first instruction, the first value including a plurality of individual values each corresponding to a hint field of the first hint register.
Dependencies are inferred from the claim text.