US 2013/0159678 A1 · Code optimization by memory barrier removal and enclosure within transaction

Abstract

A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.

Claims20

Dependent claims

A method comprising:

receiving, by a processor, a code section of a computer program to be executed by a computing device, the code section including one or more memory barrier instructions;
determining, by the processor, whether the code section satisfies one or more thresholds;
responsive to determining that the code section satisfies the thresholds, modifying the code section by:
enclosing, by the processor, the code section within a transaction that employs hardware transactional memory of the computing device, such that an entirety of the code section is executed or none of the code section is executed;
and,
removing, by the processor, the memory barrier instructions from the code section.

3 more elements

A computer program product comprising a computer-readable storage medium having computer-readable code embodied therein and executable by a processor to modify a code section of a computer program to be executed by a computing device, the code section including one or more memory barrier instructions, wherein modifying the code section comprises:

enclosing the code section within a transaction that employs hardware transactional memory of the computing device, such that an entirety of the code section is executed or none of the code section is executed;
and,
removing the memory barrier instructions from the code section.

A system comprising:

a processor;
a storage device to store a code section of a computer program to be executed by a computing device, the code section including one or more memory barrier instructions;
a software component executable by the processor to modify the code section by:
enclosing the code section within a transaction that employs hardware transactional memory of the computing device, such that an entirety of the code section is executed or none of the code section is executed;
and,
removing the memory barrier instructions from the code section.

3 more elements

Dependencies are inferred from the claim text.

Code optimization by memory barrier removal and enclosure within transaction

Life of this patent

Code optimization by memory barrier removal and enclosure within transaction

Life of this patent

Abstract

Claims20