US 2013/0159676 A1Published application

Instruction set architecture with extended register addressing

AssigneeInternational Business Machines Corporation

InventorsAdam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs

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Abstract

A method and circuit arrangement selectively repurpose bits from a primary opcode portion of an instruction for use in decoding one or more operands for the instruction. Decode logic of a processor, for example, may be placed in a predetermined mode that decodes a primary opcode for an instruction that is different from that specified in the primary opcode portion of the instruction, and then utilize one or more bits in the primary opcode portion to decode one or more operands for the instruction. By doing so, additional space is freed up in the instruction to support a larger register file and/or additional instruction types, e.g., as specified by a secondary or extended opcode.

A method of executing instructions in a processor of the type including an auxiliary execution unit, the method comprising:

receiving first and second instructions from an instruction stream, wherein the first and second instructions are members of an instruction set architecture defined for the processor, and wherein each instruction in the instruction set architecture includes a primary opcode portion and an operand portion;
in response to receiving the first and second instructions:
decoding the first and second instructions by determining primary opcodes for each of the first and second instructions from the respective primary opcode portions thereof and determining at least one operand for each of the first and second instructions from the respective operand portions thereof;
storing a primary opcode in a primary opcode register in response to decoding the first instruction;
and
storing a count in a count register in response to decoding the second instruction;
and
after receiving the first and second instructions, receiving a plurality of auxiliary instructions from the instruction stream, wherein a number of auxiliary instructions in the plurality of auxiliary instructions is equal to the count stored in the count register by the second instruction;
and
for each auxiliary instruction among the plurality of auxiliary instructions:
determining that the count register stores a non-zero value;
decoding a primary opcode for such auxiliary instruction based upon the primary opcode stored in the primary opcode register;
decoding a secondary opcode for such auxiliary instruction from a secondary opcode portion of such auxiliary instruction, wherein the secondary opcode portion is different from the primary opcode portion;
decoding a plurality of operands for such auxiliary instruction by concatenating at least one most significant bit for each operand encoded in the primary opcode portion of such auxiliary instruction with a plurality of least significant bits for each operand encoded in the operand portion of such auxiliary instruction;
executing such auxiliary instruction in the auxiliary execution unit using the primary opcode, secondary opcode and plurality of operands decoded from such auxiliary instruction;
and
decrementing the count register.

14 more elements

Facts

Application

13/330,804Filed 20 Dec 2011

Published

20 Jun 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/30185
Instruction operation extension or modification: according to one or more bits in the instruction, e.g. prefix, sub-opcode
G06F 9/30101
Register arrangements: special purpose registers
G06F 9/30138
Organisation of register space, e.g. banked or distributed register file: extension of register space, e.g. register cache
G06F 9/30189
Instruction operation extension or modification: according to execution mode, e.g. mode flag

Abstract

Claims25