Bitstream Buffer Manipulation With A SIMD Merge Instruction

A system comprising:

• a processor comprising:
• a plurality of registers, wherein the plurality of registers are to store packed data;
• a cache;
• an instruction fetch unit to fetch a shift right merge instruction;
• an instruction decoder to decode the shift right merge instruction, the shift right merge instruction indicating a first 32-bit source operand in a register of the plurality of registers and a second 32-bit source operand in a register of the plurality of registers, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements;
• and
• an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to:
• shift the second 32-bit source operand right by one byte;
• merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of a result that also includes,
• in a least significant portion thereof, three shifted 8-bit byte data elements of the second 32-bit source operand;
• and
• store the result in a 32-bit destination indicated by the shift right merge instruction, wherein the destination is a register of the plurality of registers;
• a Bluetooth universal asynchronous receiver/transmitter (UART) interface;
• a universal serial bus (USB) interface;
• a synchronous dynamic random access memory (SDRAM) control interface;
• and
• a flash interface.