Storing the most significant and the least significant bytes of characters at non-contiguous addresses

A computer system, comprising:

• a processor;
• and
• memory communicatively coupled to the processor, wherein the memory is encoded with instructions that when executed on the processor comprise:
• setting an indicator to indicate that all of a plurality of most significant bytes of characters in a character array are zero,
• receiving a first index and an input character comprising a first most significant byte and a first least significant byte,
• storing the first most significant byte at a first storage location and the first least significant byte at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses, wherein the storing further comprises storing the first most significant byte at the first storage location identified by a first address that comprises a base address of the character array plus the first index plus a character length of the character array and storing the first least significant byte at the second storage location identified by a second address that comprises the base address of the character array plus the first index, and
• if the first most significant byte does not equal zero, setting the indicator to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero, wherein the character array comprises the first most significant byte and the first least significant byte.