Self terminated dynamic random access memory

A method for operating a computing device, the method comprising:

• receiving a command signal for a target DRAM device from a plurality of DIMM devices from a CPU device;
• determining whether the command signal is either a read command for a read cycle or write command for a write cycle;
• maintaining an ignore state upon receiving an ODT signal by decoupling any logic operation from the ODT signal;
• and
• transferring information through a data line to the target DRAM device from the plurality of DIMM devices coupled together through a common data bus interface, while maintaining each of the other DIMM devices in a termination state to prevent any undesirable signals from traversing to the common data bus interface.

A memory system comprising a device, the device comprising:

• a bi-directional data bus line port;
• a command line port;
• an address line port;
• an array of elements coupled to the logic block;
• and
• a logic block coupled to the bi-directional data bus line port, the command line port, and the address line port, and configured with the array of elements to provide a termination state to each of a plurality of DRAM devices while allowing a selected DRAM device to have access to the bi-directional data bus line port during a read cycle or a write cycle.