Ddr receiver enable cycle training

A non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform a method, comprising:

• sampling a data strobe signal for a plurality of memory cycles;
• determining a receiver enable phase based upon the sampled data strobe signal;
• performing at least one memory write cycle and at least one memory read cycle to read data written by the at least one memory write cycle at a selected memory clock frequency;
• training at least one read data strobe cycle associated with the memory read cycle, wherein training is performed at a one-quarter memory clock periodic offset from an optimal receiver enable delay phase;
• and
• determining a correct receiver enable delay in response to a successful read data strobe training cycle.

An apparatus, comprising:

• at least one communication interface portion communicatively coupleable to at least one memory portion and to a processing device;
• and
• a first circuit portion, communicatively coupled to the at least one communication interface portion, and configured to:
• monitor a plurality of memory cycles on the at least one communication interface portion;
• determine a receiver enable cycle phase;
• and
• train a receiver enable cycle without using receiver enable seed.