Serial Interface for FPGA Prototyping

A method comprising:

• at a first FPGA, receiving parallel advanced crossbar interconnect (AXI) data signals corresponding to a data read request from an AXI component, the AXI data signals identifying an address from which data is to be read;
• packetizing the AXI data signals of the data read request into an AXI read packet;
• transmitting the AXI read packet via a serial link to a second FPGA;
• receiving an AXI read complete packet from the second FPGA via the serial link, the AXI read complete packet including the requested data;
• extracting the requested data from the AXI read complete packet;
• and
• providing the requested data to the AXI component.

An advanced crossbar interconnect (AXI) bridge structure for enabling serial communication between field programmable gate arrays (FPGA) in a system-on-chip, the AXI bridge structure comprising:

• a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA;
• a transmit (TX) engine configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link;
• a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract additional AXI data signals from the additional AXI data packet;
• and
• the parallel interface further configured to provide the additional AXI data signals to the AXI component.