Parity error detection verification
AssigneeAdvanced Micro Devices, Inc.
InventorChristopher E. Hsiong
Life of this patent
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Abstract
A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.
Claims20
A method of simulating a circuit design on a computing system comprising:
- selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design;
- and
- inserting the parity error in the first memory location during simulation of the circuit design.
A non-transitory computer-readable storage medium encoding instructions executable by a computing system to cause the computing system to:
- determine that a first memory location of a circuit design is associated with a higher probability of being read than a second memory location of the circuit design;
- and
- cause a parity error associated with the first memory location during simulation of the circuit design.
A method of simulating a circuit design on a computing system, the method comprising:
- in response to a register of a register file being included in an architectural-to-physical register mapping of a simulation of the circuit design, introducing a parity error associated with the register in the simulation.
Dependencies are inferred from the claim text.