US 2013/0158905 A1Published application

Test apparatus and test method

AssigneeAdvantest Corporation

InventorMasaru Tsuto

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Abstract

A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.

Claims4

Dependent claims

A test apparatus comprising:

a vector pattern generating unit configured to generate a vector pattern which specifies a vector of a device under test;
a synchronization pattern generating unit configured to generate a synchronization pattern required for a clock recovery unit which has been built into the device under test to maintain a link with an external circuit;
a gate signal generating unit configured to generate a gate signal which is asserted during a period of time in which the vector pattern is to be supplied to the device under test;
and
a pattern selecting unit configured to receive the vector pattern, the synchronization pattern, and a control signal which specifies a mode, and to operate such that, in a first mode, it outputs the vector pattern during a period of time in which the gate signal is asserted and outputs a fixed output level during a period of time in which the gate signal is negated, and such that, in a second mode, it outputs the vector pattern during a period of time in which the gate signal is asserted and outputs the synchronization pattern during a period of time in which the gate signal is negated.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/734,211Filed 4 Jan 2013
Priority: 7 Jul 2010
Published: 20 Jun 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 17/00
Digital computing or data processing equipment or methods, specially adapted for specific
G01R 31/2601
Testing of individual semiconductor devices: apparatus or methods therefor
G01R 31/31908
Tester configuration: tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
G01R 31/31726
Timing aspects, e.g. clock distribution, skew, propagation delay: synchronization, e.g. of test, clock or strobe signals; Signals in different…

Family

Application13/734,211Continuation
US 9,262,376 B2Related patent
US 2013/0158905 A1This patent

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