Structure and method for thermal treatment with epitaxial sicp thermal stability improvement

A method, comprising:

• forming a dummy gate stack on a substrate that includes a channel region underlying the dummy gate stack and includes source/drain (S/D) regions interposed by the channel region;
• forming source and drain extension (SDE) features in the S/D regions;
• performing a first thermal annealing process to the substrate for SDE activation;
• etching the substrate in the S/D regions to form recessed regions in the substrate;
• forming in-situ doped features on the recessed regions;
• removing the dummy gate stack from the channel region;
• forming a high k dielectric material layer on the substrate and within the channel region;
• and
• thereafter applying, to the substrate, a millisecond annealing process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

A method of making a semiconductor structure, comprising:

• forming a dummy gate stack on a semiconductor substrate that includes a channel region and source/drain (S/D) regions interposed by the channel region;
• etching the substrate in the S/D regions to form recessed regions in the semiconductor substrate;
• forming in-situ phosphorous doped silicon carbide features on the recessed regions;
• forming an interlayer dielectric (ILD) layer on the semiconductor substrate and the dummy gate stack;
• removing the dummy gate stack, resulting in a gate trench in the ILD layer;
• forming a high k dielectric material layer in the gate trench;
• and
• performing a millisecond annealing (MSA) process to the high k dielectric material, wherein the MSA process includes a thermal profile having a first thermal wavelet and a second thermal wavelet separated from the first thermal wavelet by a charging time.