High speed counter apparatus

Abstract

Disclosed is a high speed counter apparatus. The high speed counter apparatus includes a first counter configured to perform a count on the lower bits of the final output signal in response to a first clock signal, a second counter configured to perform a count on the upper bits of the final output signal in response to a second clock signal, and a clock signal generator configured to generate the second clock signal from the first clock signal. In accordance with the present invention, power consumption and a bottleneck phenomenon in an upper bit counter can be reduced because a second clock signal for operating the upper bit counter is synchronized with a first clock signal for operating the lower bit counter at a frequency lower than that of the clock signal for operating the lower bit counter.

Dependencies are inferred from the claim text.