Electrical fuse memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSung-Chieh LIN, David YEN, Wei-Li LIAO, Jiann-Tseng HUANG, Kuoyuan (Peter) HSU
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Abstract
A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
Claims20
A method of reading an eFuse in a column of eFuse memory cells, the method comprising:
- electrically disconnecting a first end of the eFuse from a first electrical path;
- activating a second electrical path between a second end of the eFuse and a node to bypass a third electrical path, the third electrical path comprising a diode device between the second end of the eFuse and the node;
- and
- turning on a footer coupled with the node.
A method of programming an eFuse in a column of eFuse memory cells, the method comprising:
- electrically coupling a first end of the eFuse with a first electrical path;
- deactivating a second electrical path between a second end of the eFuse and a node;
- turning on a footer coupled with the node;
- and
- changing the eFuse from a low-resistance state to a high-resistance state by a current flow through the first electrical path, the eFuse memory cell, a third electrical path, and the footer, the third electrical path comprising a diode device between the second end of the eFuse and the node.
A memory array, comprising:
- a plurality of eFuse memory cells arranged in columns and rows, each of the plurality of eFuse memory cells comprising:
- an eFuse having a first end coupled to a bit line of a corresponding one of the columns and a second end;
- a diode coupled between the second end of the eFuse and a node of the corresponding eFuse memory cell;
- and
- a transistor coupled between the second end of the eFuse and the node;
- a plurality of footers, each of the plurality of footers coupled to the nodes of the eFuse memory cells of a corresponding one of the rows;
- a first set of word lines, each of the first set of word lines coupled to gate terminals of the transistors of the eFuse memory cells of a corresponding one of the rows;
- and
- a second set of word lines, each of the second set of word lines coupled to a corresponding one of the footers.
Dependencies are inferred from the claim text.