Fabrication and testing method for nonvolatile memory devices

A semiconductor wafer, comprising:

• a plurality of master chips arranged in a row on the wafer, each master chip including a power supply circuit provides a power supply voltage;
• and
• a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing.

A method of fabricating semiconductor devices, comprising:

• fabricating a plurality of master chips arranged in a row on a wafer, wherein each master chip includes a master control circuit that provides a control signal;
• and
• fabricating a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips on the wafer, wherein each slave chip includes a slave control circuit responsive to the control signal provided by the corresponding master chip, wherein the fabricating the plurality of master chips and fabricating the plurality of slave chips is performed by a common set of fabrication processes.