Methodology for Recovering Failed Bit Cells in an Integrated Circuit Memory
OwnerMayank Gupta, John Wuuinventors
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Abstract
A method for recovering failed bit cells in an integrated circuit memory is disclosed. In one embodiment, the method includes stress testing an integrated circuit having a memory, wherein the memory includes a plurality of bit cells. The method further includes holding at least one internal node of the selected one of the plurality of bit cells at a first predetermined state for a period sufficient to cause a shift in a threshold voltage of a transistor in the selected one of the plurality of bit cells.
Claims29
A method comprising:
- stress testing an integrated circuit having a memory, wherein the memory includes a plurality of bit cells;
- and
- holding at least one internal node of the selected one of the plurality of bit cells at a first predetermined state for a period sufficient to cause a shift in a threshold voltage of a transistor in the selected one of the plurality of bit cells.
A computer readable medium storing instructions that, when executed on an integrated circuit (IC) test system, cause the IC test system to perform a test of an IC including a memory having a plurality of bit cells, wherein testing the IC comprises:
- holding at least one internal node of the selected one of the plurality of bit cells at a first predetermined state for a period sufficient to cause a shift in a threshold voltage of a transistor in the selected one of the plurality of bit cells.
A method comprising:
- identifying selected ones of a plurality of bit cells of a memory implemented on an integrated circuit (IC), wherein the selected ones of the plurality of bit cells are identified based on having passed a test of the memory at a first operating point and having failed a test of the memory at a second operating point;
- and
- performing a test of the IC, wherein performing the test includes applying test patterns to the memory while the IC is at a temperature greater than ambient temperature;
- wherein said performing the test of the IC includes holding at least one internal node of a first of the selected ones of the plurality of bit cells at a predetermined state for a period sufficient to cause a change in a threshold voltage of a transistor in the first of the selected ones of the plurality of bit cells.
Dependencies are inferred from the claim text.