Semiconductor device having data terminal supplied with plural write data in serial

A semiconductor device comprising:

• a frequency dividing circuit configured to receive a first clock signal to generate a second clock signal having lower frequency than the first clock signal;
• a plurality of data buses;
• a data terminal supplied with a plurality of write data in serial;
• a data strobe terminal supplied with a data strobe signal;
• a serial-to-parallel conversion circuit configured to convert the write data supplied via the data terminal from serial to parallel in synchronism with the data strobe signal;
• and
• a synchronizing circuit configured to output the write data in parallel to the data buses in synchronism with the second clock signal.

A semiconductor device comprising:

• a memory cell array including a plurality of memory cells;
• a plurality of data buses receiving, in a data read mode, parallel-read-data from the memory cell array and supplying, in a data write mode, parallel-write-date to the memory cell array;
• a first clock circuit including a plurality of output nodes and configured to generate, in the data read mode, a plurality of first clock signals at the output nodes, respectively, and to generate, in the data write mode, at least one second clock signal at an associated one of the output nodes while stopping generation of clock signal or signals at remaining one or ones of the output nodes;
• a second clock circuit coupled to the output nodes of the first clock circuit and configured to produce, in the data read mode, a third clock signal in response to the first clock signals and, in the data write mode, a fourth clock signal in response to the second clock signal, the third clock signal being greater in frequency than the fourth clock signal;
• a data terminal;
• a date output circuit coupled to the data buses to convert the parallel-read-data into serial-read-data in response to the third clock signal, the data output circuit being coupled to the data terminal to drive the data terminal in response to the serial-read-data;
• and
• a data input circuit coupled to the data terminal to convert serial-write data into the parallel-write-data, the data output circuit coupled to the data buses to supply the parallel-write data to the data buses in response to the fourth clock signal.