Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorSung-Hwa OK
Life of this patent
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Abstract
A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.
Claims20
A semiconductor memory device comprising:
- an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address;
- a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal;
- a core unit configured to store the internal data in response to the column select signal;
- and
- an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.
A semiconductor memory device comprising:
- an internal command generation unit configured to generate first and second internal commands in response to an external command;
- a first command transmission unit configured to, in response to preamble period information, selectively transmit any one of the first internal command and a third internal command obtained by delaying the first internal command by a first period;
- an internal signal generation unit configured to generate a column select signal and a write enable signal in response to an external address and an internal command transmitted from the first command transmission unit;
- a strobe command generation unit configured to generate a first strobe command by delaying, in response to an internal synchronization signal, the second internal command by a second period;
- a second command transmission unit configured to, in response to the preamble period information, selectively transmit any one of the first strobe command and a second strobe command obtained by delaying the first strobe command by the first period;
- a write circuit unit configured to generate internal data corresponding to external data in response to the write enable signal and a strobe command transmitted from the second command transmission unit;
- and
- a core unit configured to store the internal data in response to the column select signal.
Dependencies are inferred from the claim text.