US 2013/0155790 A1 · STORAGE DEVICE

Abstract

Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit.

Claims15

Dependent claims

A semiconductor device comprising:

a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;
a first memory cell array comprising a first memory cell, the first memory cell being electrically connected to the first bit line and a first word line;
and
a second memory cell array comprising a second memory cell over the first memory cell array, the second memory cell being electrically connected to the second bit line and a second word line,
wherein the first bit line is provided over the first word line,
wherein the second word line is provided over the second bit line, and
wherein the first memory cell overlaps with the second memory cell.

4 more elements

A semiconductor device comprising:

a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;
a first memory cell array comprising a first memory cell comprising a first transistor, the first transistor comprising:
a first semiconductor layer;
a first source electrode and a first drain electrode over the first semiconductor layer, one of the first source electrode and the first drain electrode being electrically connected to the first bit line,
a first insulating layer over the first source electrode, the first drain electrode, and the first semiconductor layer;
and
a first gate electrode over the first insulating layer, the first gate electrode being electrically connected to a first word line;
and
a second memory cell array comprising a second memory cell comprising a second transistor, the second transistor comprising:
a second semiconductor layer;
a second source electrode and a second drain electrode over the second semiconductor layer, one of the second source electrode and the second drain electrode being electrically connected to the second bit line,
a second insulating layer over the second source electrode, the second drain electrode, and the second semiconductor layer;
and
a second gate electrode over the second insulating layer, the second gate electrode being electrically connected to a second word line,
wherein the first bit line is provided over the first word line,
wherein the second word line is provided over the second bit line, and
wherein the first memory cell overlaps with the second memory cell.

14 more elements

Dependencies are inferred from the claim text.

Storage device

Life of this patent

Storage device

Life of this patent

Abstract

Claims15