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US 2013/0155789 A1Published application
Data sensing circuit and memory device including the same
AssigneeSK hynix Inc.
InventorJong-Su KIM
Life of this patent
Estimating the term…
Abstract
An memory device includes a bit line, an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line and a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line.
Claims11
An memory device, comprising:
- a bit line;
- an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line;
- and
- a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line.
1 more element
An memory device, comprising:
- a plurality of memory cells;
- a plurality of word lines configured to control the multiple memory cells;
- a plurality of bit lines configured to transfer data of the memory cells;
- an NMOS transistor provided for each of the bit lines and configured to supply a voltage of a pull-up voltage terminal to a bit line corresponding thereto in response to a voltage level of the corresponding bit line;
- and
- a PMOS transistor provided for each of the bit lines and configured to supply a voltage of a pull-down voltage terminal to a bit line corresponding thereto in response to a voltage level of the corresponding bit line.
3 more elements
An memory device, comprising:
- a data line;
- an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the data line in response to a voltage level of the data line;
- and
- a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the data line in response to a voltage level of the data line.
1 more element
Dependencies are inferred from the claim text.