Ddr 2d vref training

A non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform a method, comprising:

• performing at least one memory operation in response to at least one instruction indicative of performing a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device;
• and
• determining a DDR memory reference voltage and a DDR memory delay time based at least upon the performed at least one memory operation.

A circuit that comprises:

• at least one communication interface portion configured to be communicatively coupled to at least one memory portion and to a processing device;
• and
• a circuit portion, communicatively coupled to the at least one communication interface portion, that comprises at least one of a hardware state machine, or an algorithm, adapted to provide instructions to the processing device to perform a double data rate (DDR) reference voltage training at least in the voltage domain.