US 2013/0155784 A1 · SEMICONDUCTOR MEMORY APPARATUS

Abstract

A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

Claims20

Dependent claims

A semiconductor memory apparatus comprising:

a first sense amplification unit comprising first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar;
and
a second sense amplification unit comprising first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied,
wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

1 more element

A semiconductor memory apparatus comprising:

a first sense amplification unit comprising first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar;
a control unit configured to generate an activated switching signal according to an activated active signal, a read signal and a write signal;
and
a second sense amplification unit comprising first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when the activated switching signal is applied,
wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/563,014Filed 31 Jul 2012

Priority

KR 10-2011-013569415 Dec 2011

Published

20 Jun 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 7/08
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: control thereof
G11C 7/065
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of latching type
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 29/12
Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing: built-in arrangements for testing, e.g.…

Semiconductor memory apparatus

Life of this patent

Semiconductor memory apparatus

Life of this patent

Abstract

Claims20