Fast-bypass memory circuit

A method to present input data at a data output of a memory circuit promptly on receiving a clock pulse in the memory circuit, the method comprising:

• delaying receipt of the clock pulse in upstream memory logic of the memory circuit;
• latching the input data in the upstream memory logic on receiving the clock pulse in the upstream memory logic;
• and
• in selection logic of the memory circuit, exposing a logic level derived from the input data before the input data is latched in the upstream memory logic, and, exposing a logic level derived from the latched input data after the input data is latched in the upstream memory logic.

A memory circuit that presents input data at a data output promptly on receiving a clock pulse, the circuit comprising:

• upstream memory logic configured to latch the input data on receiving the clock pulse;
• selection logic configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched;
• downstream memory logic configured to store the logic level exposed by the selection logic and to present the stored logic level at the data output on receiving the clock pulse;
• and
• a buffer configured to delay receipt of the clock pulse in the upstream memory logic relative to receipt of the clock pulse in the downstream memory logic.