Fast-bypass memory circuit

A method to make a level of a first data input appear promptly at an output of a memory circuit in response to a clock pulse received, the method comprising:

• driving a first control input with the clock pulse;
• triggering a flip-flop to store the level of the first data input on receipt of the clock pulse, the flip-flop configured to drive a second data input and a second control input;
• and
• in selection logic configured to receive the first and second data inputs and the first and second control inputs, driving the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs, where the output is driven to the level of the first data input on receipt of the clock pulse in the selection logic, and before the level of the first data input is stored.

A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received, the circuit comprising:

• a flip-flop triggered by receipt of the clock pulse to store the level of the first data input and configured to drive a second data input;
• a first control input driven by the clock pulse;
• a second control input driven by the flip flop;
• selection logic configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs, the output being driven to the level of the first data input on receipt of the clock pulse in the selection logic and before the level of the first data input is stored;
• and
• a buffer through which the clock pulse triggers the flip-flop, the buffer delaying the triggering of the flip-flop relative to receipt of the clock pulse in the selection logic.