Semiconductor memory device

A semiconductor memory device comprising:

• a page buffer for each bit line of a plurality of bit lines, each page buffer including,
• a latch configured to store one of data to be written to a first nonvolatile memory cell selected by a first word line of a plurality of word lines and data read from the first nonvolatile memory cell, the first nonvolatile memory cell one of a plurality of nonvolatile memory cells at intersections of the plurality of bit lines and the plurality of word lines;
• and
• a replica capacitor network including at least a first capacitor and a second capacitor connected in parallel,
• wherein the page buffer is configured to store in the replica capacitor network a voltage value of a second word line adjacent to the first word line when a second nonvolatile memory cell is turned on, the second nonvolatile memory cell connected to the second word line and written later than the first nonvolatile memory cell, and the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell according to the voltage value stored in the replica capacitor.

A page buffer for each of a plurality of bit lines included in a memory array in a semiconductor memory device, the page buffer comprising:

• a latch configured to store one of data to be written to a first nonvolatile memory cell in the memory array and data read from the first nonvolatile memory cell based on a clock signal, the first nonvolatile memory cell selected by a first word line;
• a comparator configured to compare a first word line voltage to a reference voltage, the output of the comparator being input as the clock signal to the latch;
• and
• a replica capacitor network configured to store a second word line voltage of a second word line when a second nonvolatile memory cell is turned on, the second word line adjacent to the first word line, the replica capacitor network configured to vary the first word line voltage compared by the comparator.