Circuit and method for spin-torque mram bit line and source line voltage regulation

A method for writing to and reading from a spin-torque MRAM having a first source line, a second source line, a first bit line, a second bit line, each of a first plurality of magnetic tunnel junction cells coupled in series with one each of a plurality of word line select transistors between the first source line and the first bit line, and a second plurality of magnetic tunnel junction cells coupled in series with one each of a second plurality of word line select transistors between the second source line and the second bit line, comprising:

• applying a first voltage at each of the first source line, first bit line, second source line, and second bit line;
• applying a word line voltage to one word line select transistor of each first and second pluralities of word line select transistors;
• isolating the first source line and first bit line from the first voltage;
• applying a second voltage at one of the first bit line or first source line;
• applying a third voltage at the other of the first bit line or first source line at which the second voltage is applied;
• isolating the third voltage from the first bit line or first source line at which it was applied;
• isolating the second voltage from the first bit line or first source line at which it was applied;
• and
• reapplying the first voltage at each of the first source line and second source line.

A spin-torque MRAM, comprising:

• a first source line;
• a second source line;
• a first bit line;
• a second bit line;
• a first plurality of first magnetic bit cells each coupled between the first source line and the first bit line;
• a second plurality of second magnetic bit cells each coupled between the second source line and the second bit line;
• a word line driver configured to selectively activate one of the first magnetic bit cells and one of the second magnetic bit cells;
• a column selection circuit coupled to each of the first and second source lines and the first and second bit lines and configured to apply a precharge voltage to the first and second source lines and the first and second bit lines;
• sense amplifiers and write drivers circuitry coupled to the column selection circuitry;
• and
• column circuit drivers circuitry coupled to the sense amplifiers and write drivers circuitry and the column selection circuitry.