Back to results
US 2013/0155762 A1Published application
Random access memory architecture for reading bit states
AssigneeEverspin Technologies, Inc.
InventorDimitri Houssameddine
Life of this patent
Estimating the term…
Abstract
An architecture and method includes providing an oscillatory signal through each magnetic tunnel junction (MTJ), or in a line adjacent each MTJ, in a magnetoresistive random access memory array. A rectified signal appearing across each MTJ is measured and compared to a reference signal for determining the state of the MTJ.
Claims21
A method of reading a magnetic tunnel junction cell, the method comprising:
- applying an oscillating signal to the magnetic tunnel junction cell;
- measuring the rectified signal across the magnetic tunnel junction cell;
- comparing the rectified signal with a reference signal;
- and
- determining the state of the magnetic tunnel junction cell based on the comparing step.
2 more elements
A random access memory architecture comprising:
- a plurality of magnetic memory bits, each magnetic memory bit having a programmable state comprising one of a first resistance state and a second resistance state;
- a sensing unit configured to apply an oscillating signal to each of the magnetic memory bits;
- and
- a read logic selectively coupled to each of the magnetic memory bits and configured to sense whether each magnetic memory bit is in the first or second resistance state.
1 more element
A magnetoresistive random access memory comprising:
- an array of memory cells, each memory cell having a programmable state consisting of one of a first resistance state and a second resistance state;
- a sensing unit configured to apply an oscillating signal to each of the memory cells;
- and
- a read logic configured to measure a rectified signal across each of the memory cells and compare the rectified signal with a reference signal to determine if the cell is in the first or second resistance state.
1 more element
Dependencies are inferred from the claim text.