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US 2013/0155759 A1Published application
Test Structures, Methods of Manufacturing Thereof, Test Methods, and MRAM Arrays
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYa-Chen Kao, Tien-Wei Chiang, Chun-Jung Lin
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Abstract
Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.
Claims20
A test structure comprising:
- a magnetic random access memory (MRAM) cell including a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ;
- a test node coupled between the MTJ and the transistor;
- and
- a contact pad coupled to the test node.
1 more element
A method of manufacturing a test structure, the method comprising:
- forming a plurality of magnetic random access memory (MRAM) cells over a workpiece, each MRAM cell including a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ;
- coupling a test node to one of the plurality of MRAM cells between the MTJ and the transistor;
- and
- coupling a contact pad to the test node.
1 more element
A testing method, including:
- providing a test structure, the test structure comprising a magnetic random access memory (MRAM) cell including a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ, the test structure comprising a test node coupled between the MTJ and the transistor, wherein the test structure is coupled to a bit-line, a word-line, and a select-line and is disposed over a substrate;
- and
- performing a test on a portion of the test structure using a combination of at least two of the test node, the bit-line, the word-line, the select-line, and the substrate.
Dependencies are inferred from the claim text.