Circuit and method for generating a sense amplifier enable signal based on a voltage level of a tracking bitline

A static random access memory (SRAM) circuit comprising:

• at least one column of SRAM storage cells;
• read/write circuitry coupled to the column of SRAM storage cells to access the column of SRAM storage cells, the read/write circuitry comprising a sense amplifier configured to read data of the column of SRAM storage cells upon receipt of a sense amplifier enable (SAE) signal;
• and
• timing circuitry configured to generate the SAE signal in response to a control signal, the timing circuitry comprising:
• a first tracking bit line;
• a second tracking bit line electrically connected to the first tracking bit line;
• a tracking cell having a driving terminal and a non-driving terminal, the non-driving terminal being connected to the second tracking bit line, and the driving terminal being connected to the first tracking bit line and configured to selectively charge or discharge a voltage on the first tracking bit line in response to a control signal;
• and
• a control logic circuit coupled to the first tracking bit line and configured to generate the SAE signal in response to the voltage level on the first tracking bit line.

A method of generating a sense amplifier enable (SAE) signal for a static random access memory (SRAM) circuit in response to a control signal, the SRAM circuit being configured to have a proper read functionality a predetermined delay time after activation of the control signal, the method comprising:

• generating a tracking signal by a tracking cell in response to the control signal by selectively charging or discharging a voltage of a first tracking bit line coupled to a driving terminal of the tracking cell and a second tracking bit line coupled to a non-driving terminal of the tracking cell and electrically coupled to the first tracking bit line;
• and
• generating the SAE signal according to the tracking signal, the SAE signal generated by control logic circuitry coupled to the tracking bit line,
• the tracking signal being activated a read timing after activation of the control signal, the read timing being a function of a tracking capacitance charged or discharged by the tracking cell, the first tracking bit line and the second tracking bit line being arranged to have the tracking capacitance sufficient to allow the read timing equal to or greater than the predetermined delay time.