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US 2013/0155753 A1Published application
Method for implementing spare logic of semiconductor memory apparatus and structure thereof
AssigneeSK hynix Inc.
InventorsYoung Suk MOON, Yong Kee KWON
Life of this patent
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Abstract
A method for implementing a spare logic of a semiconductor memory apparatus includes the steps of: forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively; and performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the independent contact conductive layers formed in the power line and the active area.
Claims20
A method for implementing a spare logic of a semiconductor memory apparatus, comprising the steps of:
- forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively;
- and
- performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the contact conductive layers formed in the power line and the active area.
A spare logic of a semiconductor memory apparatus, comprising:
- a power line having one or more contact conductive layers formed therein, on which metal programming is to be performed;
- and
- an active area having one or more contact conductive layers formed therein, which are configured to be electrically coupled to the one or more contact conductive layers of the power line through the metal programming.
Dependencies are inferred from the claim text.