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US 2013/0155752 A1Published application
Wiring configuration of a bus system and power wires in a memory chip
AssigneeElpida Memory, Inc.
InventorsMaksim Kuzmenka, Dirk Scheideler, Kai Schiller
Life of this patent
Estimating the term…
Abstract
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip.
Claims20
A device comprising:
- a signal line extending from a first node to a second node to transfer a signal therethrough;
- a power line supplied with a power voltage, the power line extending along the signal line to have third and fourth nodes corresponding respectively to the first and second nodes of the signal line;
- and
- a control circuit configured to form a first electrical path between the first node of the signal line and the third node of the power line and a second electrical path between the second node of the signal line and the fourth node of the power line when the signal is free from being transferred through the signal line.
1 more element
A device, comprising:
- a first signal line;
- a second signal line;
- and
- a control circuit configured to transfer a first data signal on the first signal line and short the second signal line with the power supply line during the first period when not permitting a data to be transferred on the second signal line, the control circuit further being configured to transfer a second data signal on the second signal line during a second period different from the first period.
1 more element
A device comprising:
- a first pad for a first power source;
- a second pad for a second power source;
- a first group of pads;
- a second group of pads;
- an interface logic connected to the first and second pads, and the first and second groups of the pads;
- a memory array;
- an array control logic configured to communicate with the memory array;
- a first power source line provided between the interface logic and the array control logic to receive the first power source from the first pad;
- a second power source line provided between the interface logic and the array control logic to receive the second power source from the second pad;
- a plurality of data bus lines provided between the interface logic and the array control logic to transfer data between the first group of pads and the memory array;
- and
- a plurality of configuration bus lines provided between the interface logic and the array control logic to transfer configuration information from the second group of pads to the array control logic,
- wherein the interface logic controls to transfer configuration information through the configuration bus lines in a first mode;
- wherein the interface logic controls to short a first one of the configuration bus lines with the second power line in a second mode.
11 more elements
Dependencies are inferred from the claim text.