Memory devices having break cells

A method, comprising:

• connecting a first subset of bit cells of a bit cell array to a first voltage when the first subset of bit cells cell array is in a first operating mode;
• connecting the first subset of bit cells to a second voltage when the first subset of bit cells is in a second operating mode;
• connecting a second subset of bit cells of the bit cell array to the first voltage when the second subset of bit cells is in the first operating mode;
• and
• connecting the second subset of bit cells to the second voltage when the second subset of bit cells is in the second operating mode,
• wherein the first and second subsets of bit cells are electrically separated from one another by a break cell such that the first and second subsets of bit cells are controlled independent of one another.

A semiconductor memory, comprising:

• a first break cell electrically separating a first subset of bit cells from a second subset of bit cells of a cell array;
• a first power switch configured to connect the first subset of bit cells to a first voltage during a first operating mode and to a second voltage that is different from the first voltage during a second operating mode;
• and
• a second power switch configured to connect the second subset of bit cells to the first voltage during the first operating mode and to the second voltage during the second operating mode,
• wherein the first and second power switches are controlled independently such that the first subset of bit cells can be in a different operating mode from the second subset of bit cells at a given point in time.