Semiconductor storage device

A semiconductor storage device comprising:

• a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element;
• and
• a control circuit selectively driving the first and second wirings,
• in applying, by the control circuit, a first voltage to the first wirings and a second voltage lower than the first voltage to the second wirings to apply a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings,
• the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array,
• the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal are positioned apart from a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal, with other first wirings interposed between the first and second set in the memory cell array, and
• a plurality of sets of the first wirings being repeatedly arranged in the memory cell array, each of the first wirings in one of the plurality of sets being specified by different ones of the address signals.

A semiconductor storage device comprising:

• a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element;
• and
• a control circuit selectively driving the first and second wirings,
• in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between multiple ones of the first wirings and one of the second wirings,
• the plurality of memory cells connected to one of the second wirings, on which memory cells operations are performed simultaneously, being separately arranged with other memory cells interposed therebetween in a direction in which the second wiring extends,
• the memory cells being arranged such that a first set of the plurality of memory cells specified and performed operation at the same time by a first address signal are positioned apart from a second set of the plurality of memory cells specified and performed operation at the same time by the first address signal, with other memory cells interposed between the first and second set in the memory cell array, and
• a plurality of sets of the memory cells being repeatedly arranged in the memory cell array, each of the memory cells in one of the plurality of sets being specified by different ones of address signals.

A semiconductor storage device comprising:

• a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings each of the memory cells having a variable resistance element;
• and
• a control circuit selectively driving the first and second wirings,
• in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings,
• the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array,
• the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal and a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal are arranged in the memory cell array so that they exhibit a reflectional symmetry with respect to a line of symmetry axis passing through the center of the memory cell array and in parallel to the first wirings.

A semiconductor storage device comprising:

• a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element;
• and
• a control circuit selectively driving the first and second wirings,
• in applying, by the control circuit, a first voltage to the first wirings and a second voltage lower than the first voltage to the second wirings to apply a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings,
• the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array,
• the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal and a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal are arranged in the memory cell array so that they exhibit a reflectional symmetry with respect to a line of symmetry axis passing through the center of the memory cell array and in parallel to the first wirings.

A semiconductor storage device comprising:

• a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element;
• and
• a control circuit selectively driving the first and second wirings,
• in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between multiple ones of the first wirings and one of the second wirings,
• the plurality of memory cells connected to one of the second wirings, on which memory cells operations are performed simultaneously, being separately arranged with other memory cells interposed therebetween in a direction in which the second wiring extends,
• the memory cells being arranged such that a first set of the plurality of memory cells specified and performed operation at the same time by a first address signal and a second set of the plurality of memory cells specified and performed operation at the same time by the first address signal are arranged in the memory cell array so that they exhibit a reflectional symmetry with respect to a line of symmetry axis passing through the center of the memory cell array and in parallel to the first wirings.