Content addressable memory

A content-addressable memory (CAM) comprising:

• a plurality of data lines;
• a plurality of CAM cells, each of the plurality of CAM cells comprising an output and adapted to output a logic state on the output;
• the logic state on the output being based on a logic state of a respective data line associated with the respective CAM cell and data stored in the respective CAM cell;
• and
• a summary circuit having a plurality of logic gates and an output, the plurality of logic gates are configured to generate a logic state on the output of the summary circuit based on logic states of the outputs of the plurality of CAM cells,
• wherein the plurality of logic gates are arranged as a plurality of levels of logic gates, each logic gate of at least one level of the plurality level of logic gates comprises an output pin and an odd-number of input pins.

A summary circuit, comprising:

• a first level of logic gates having inputs each configured to receive an output of a corresponding one of a plurality of content-addressable memory (CAM) cells;
• and
• a second level of logic gates having inputs each configured to receive an output of a corresponding one of the first level of logic gates,
• wherein each logic gate of the first level of logic gates, or each logic gate of the second level of logic gates, comprises an even number of input/output pins.