Distributed resonant clock grid synthesis
AssigneeThe Regents of the University of California Office of Technology Transfer
InventorMatthew Guthaus
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AssigneeThe Regents of the University of California Office of Technology Transfer
InventorMatthew Guthaus
Estimating the term…
A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained.
A method of designing VLSI clock distribution networks, comprising the steps of:
A system for designing VLSI clock distribution networks, including:
A semiconductor device having a clock grid, comprising:
Dependencies are inferred from the claim text.